Tuesday, May 22nd 9:00 am – 5:30 pm
For abbreviated agenda, click here

Keynote Speaker: Mark T. Bohr, Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration, Intel Corporation
Mr. Bohr’s keynote will open the conference and will be focused on Intel's recent announcement of High-k technology and the beneficial impact it will have on the future of the semiconductor industry.

Session One: Advances in Computer Technology
Session Chair: Mark T. Bohr, Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration, Intel Corporation

45nm Next-Generation Intel Core Microarchitecture (Penryn)
presented by Steve Fischer, Senior Principal Engineer, Intel Corporation
This presentation will discuss major new architectural features, including advanced power management, performance enhancing microarchitectural improvements, and an overview of the new SSE4 instruction set which are part of Intel's upcoming Penryn (codename) family of processors which are based on Intel’s leading 45nm Hi-K metal gate silicon process enabling higher performance within a lower power envelope.

Beyond Multi-core: The Dawning of the Era of Tera
presented by Jim Held, Intel Fellow & Director of Intel Tera-scale Computing Research, Intel Corporation
The Intel Tera-scale Computing Research Program is a worldwide research effort to create platforms for the next decade with 10s to 100s of cores and capabilities only dreamt of today. Learn about Intel’s research vision and how an 80-core research processor commences the “Era of Tera” with teraflops performance, a terabit/second on-chip interconnect fabric, and remarkable energy efficiency.

Reinventing Multi-core Cache & Memory: Architecture, Performance and QoS
presented by Ravi Iyer, Intel Principal Research Scientist, Intel Corporation
From Intel's work on large-scale CMP platforms and "tera-scale" workload scenarios in the next decade comes an analysis of multi-workload scenarios in both server and client environments emphasizing cache & memory scalability, performance and QoS considerations. In this discussion, we will highlight the opportunities and challenges for 2010+ multi-core cache/memory hierarchies as well as potential solutions.

Session Two: Power Reduction Technologies
Session Chair: Jim McGregor, Research Director, In-Stat

Striking the Balance: Managing Performance and Power Efficiency in Next-Generation Mobile Platforms
presented by Maurice Steinman, AMD Fellow, AMD
AMD will introduce a new method of power savings in which the processor is freed from reliance on operating system software to coordinate the use of energy.

New Semiconductor Technology Enhances Drive Current, Lowers Leakage
presented by Robert J. Mears, President & CTO, MEARS Technologies
MEARS Technology will present a method of device scaling below 45nm, that incorporates a new technique to enhance drive current and mitigate microprocessor gate leakage through insertion of a high-mobility epitaxial silicon-channel replacement layer, which involves no new elements in the fabrication process.

Session Three: Processors on the Move
Session Chair: Max Baron, Principal Analyst, Microprocessor Report, In-Stat

Automotive-Qualified Multicore Microprocessors for Telematics, Navigation and Industrial Control Systems
presented by Jeff Maguire, Chief Architect, Freescale Semiconductor
Freescale will unveil two new SoC microprocessors designed for the telematics and automotive navigation markets, as well as networked industrial control applications.

A Processor Chipset for Real-Time Image Analysis
presented by Axel Kloth, CTO & Vice President of Engineering, Parimics, Inc.
Parimics will introduce the architecture, design and implementation of a semiconductor processor chipset designed to perform image analysis.

SH-Navi2V: A Car Navigation Processor Employing a 38.4GOPS Image Recognition Engine
presented by Toru Baji, Department Manager, Automotive Application Engineering Dept. 2, Renesas Technology Corporation, co-authored by Yoshiyuki Matsumoto, Senior Engineer, Car Information System Design Dept., Renesas & Shoji Muramatsu, Hitachi Research Lab.
Renesas will disclose details of its car navigation processor employing a superscalar CPU Core SH4A and a parallel image recognition engine.

Keynote Speaker: Eisuke Miki, President and CEO, DoCoMo Communications Laboratories USA, Inc.
NTT DoCoMo's keynote will open the second conference day to inform attendees on the status of Super 3G and 4G cellular phone technologies, and the tests and experiments carried out to date. The service providers' requirements of functions that must be provided by cell phone processors during the next few years will also be addressed. The migration toward 4G providing up to 1.0 Gb/s data communications will affect all computers, not just cell phones.

Session Four: Video & Graphics Multicore Architectures
Session Chair: Max Baron, Principal Analyst, Microprocessor Report, In-Stat

A Dual-Core Dynamically Reconfigurable Engine Employs 955 Parallel Processing Elements
presented by Tomoyoshi Sato, Vice President & CTO, IPFlex Inc.
This presentation is the first disclosure of IPFlex’s dynamically reconfigurable processor targeted to provide high-performance programmable processing that is difficult to obtain via conventional ASICs. The presentation will provide detail on the engine’s processing capability plus application examples.

NVIDIA CUDA Software and GPU Parallel Computing Architecture
presented by John Nickolls, Director of Architecture, NVIDIA
This presentation will be a first detailed disclosure of NVIDIA’s CUDA parallel software and NVIDIA's Massively Multi-Threaded Architecture. The new parallel architecture targets high throughput, data intensive processing.

Making Parallel Processing Simple -- Storm-1: A Massively Parallel C-programmable 112 GMACS Stream Processor
presented by Bill Dally, Co-founder, Chairman & Chief Scientist, Stream Processors, Inc.
SPI will announce and describe the new SP16HP-G220, the flagship device of the Storm-1 family, featuring leading signal processing capabilities of up to 112 GMACS for 16-bit operands or 440 GOPS for 8-bit data.

A Software-Configurable Processor Architecture for Video Security
presented by Robert K. Beachler, Vice President, Product Planning, Stretch Inc.
This presentation is a first disclosure of Stretch's second generation software-configurable processor architecture and how it has been optimized for video surveillance applications. The new architecture has been created specifically to meet the performance demands of high resolution, intelligent, network based security environments.

Session Five: Embedded Processors & Cores
Session Chair: Tom Halfhill, Senior Editor, Microprocessor Report, In-Stat

Titan-A Low Power High Performance Core Based on the Power Architecture
presented by Joe Chang, Chief Architect, AMCC, co-authored by Steve Horne, Founder and Director of Research Technology, Intrinsity
AMCC will introduce for the first time, details of its new Titan superscalar microprocessor architecture.

A New ARM Processor for Synthesis on FPGA
presented by Ian Devereux, Director of Technology, Processor Division, ARM
This paper provides an overview of the technology applied to enable the creation of an ARM processor designed for synthesis on FPGA.

ARMv7 Architecture Receives Multi-processor Extensions
presented by John Goodacre, Program Manager, Multiprocessing, ARM
This presentation is the first disclosure of new extensions to the ARMv7 architecture that form the basis for future ARM multi-processors. It also explores the fundamental requirements of multi-processor systems and reviews existing hardware and software implementations.

New Area and Power – Efficient MIPS Processors Achieve High Performance
presented by Vidya Rajagopalan, Director of Engineering, MIPS Technologies, Inc.
MIPS Technologies will launch its new generation of single-threaded, high-performance processor cores designed to optimize die area and power.

Session Six: Application-Specific Platforms
Session Chair: Max Baron, Principal Analyst, Microprocessor Report, In-Stat

The Scorpion Mobile Application Microprocessor
presented by Thomas Sartorius, Principal Architect, Qualcomm
Qualcomm will introduce its power-efficient Gigahertz microprocessor core aimed at a broad range of mobile applications.

Snapdragon, High-Performance Mobile Platform
presented by Mark Schaffer, Senior Staff Engineer/Architect, Qualcomm
The Snapdragon High-Performance Mobile Platform is designed to close the performance gap between the PC and mobile handsets.

A Dual-Core Video Decoder/Encoder
presented by Dennis Moolenaar, Member of Technical Staff, Tensilica, Inc.
Tensilica will reveal the implementation details of its Diamond Standard 388VDO Video Engine--a preconfigured video IP core consisting of two interconnected Tensilica Xtensa LX processor cores.